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DATA SHEET
PD6464A,6465
ON-SCREEN CHARACTER DISPLAY CMOS LSI FOR 12-LINE, 24-COLUMN DECK-TYPE VCR
MOS INTEGRATED CIRCUIT
The PD6464A,6465 are CMOS LSIs for on-screen character display that control various display systems (such as tape counters) including the program screens of deck-type VCRs and LD players. These LSIs are used in combination with a microcomputer. It can display characters each consisting of 12 (horizontal) by 18 (vertical) dots. Some chinese characters and some pictograms can also be displayed by combining two or more characters. The PD6464A,6465 include a power-ON clear function and a video RAM batch clear command that mitigate the workload of the host microcomputer. It also has a synchronization separator and a x4 multiplier on chip, eliminating the need of connecting an external separator IC and a crystal resonator, which reduces the mounting area and the total cost.
FEATURES
* * * * * * * * Video signal input/output Number of display characters Number of character types Character size Character color Background Dot matrix Blinking : : : : : : : : Composite video signal 12 lines, 24 columns (288 characters) 128 (PD6464A)/256 (PD6465) (ROM). Variable by mask code option. 1 dot/1 line. 2 lines (field) can be displayed in line units. White (single color) No background, black framing, black-on-white, and black filling 12 (horizontal) x 18 (vertical) dots without gap between adjacent characters Blinking can be turned ON/OFF in character units. Blinking ratio is 1:1. Blinking frequency is selectable from about 0.5 Hz, 1 Hz, and 2 Hz in screen units. Can support VCRs with S pins if external mixer is connected because character signal and blanking signal output pins are provided. Video RAM data are cleared by video RAM clear command and power-ON clear function. NTSC/PAL/PAL-M/SECAM/PAL-N (PD6464A only) Synchronization separation circuit for composite synchronizing signal and x4 multiplier Serial input type of 8-bit variable word length
* Character signal output: * Video RAM data clear * Supported video signal method * Internal circuit * Interface with microcomputer * Supply voltage
: : : : :
: +5 V, single power supply
ORDERING INFORMATION
Part Number Package 24-pin plastic shrink DIP (300 mil) 24-pin plastic shrink DIP (300 mil) 24-pin plastic SOP (375 mil) 24-pin plastic SOP (375 mil)
PD6464ACS-xxx PD6465CS-xxx PD6464AGT-xxx PD6465GT-xxx
Remark xxx : ROM code suffix (CS-001, GT-101 : NEC standard device)
The information in this document is subject to change without notice. Document No. S11043EJ4V0DS00 (4th edition) Date Published May 1998 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1995, 1996
Video RAM
Data selector
Background control data register
Horizontal size counter
Horizontal position counter
Horizontal address counter
Character data 7 bits ( PD6464A) 8 bits ( PD6465) x 288 words
Blink data 1 bit x 288 words
Vertical address register OSCIN
Oscillation circuit
6 LOSCOSCOUT
Timing generator
Vertical size counter
Vertical position counter
Vertical address counter
5
Character generator ROM 12 x 18 bits x 128 words (PD6464A) 256 words (PD6465)
COSCIN
COSCOUT
Synchronization signal generator x 4 multiplier/ 4fSC Crystal oscillation circuit Synchronization signal separation circuit
Mode selection
Output controller
Display control data register
2
DATA 3 CLK 1 Data input shift register Instruction decoder CS 2 Data buffer register Control signal 4 VDD 8 GND 19 TEST 7 PCL External/ internal register NTSC/ PAL/ PAL-M/ SECAM/ PAL-NNote register Character size register Horizontal address register Write address counter 17 CSYIN 15 16 HSYO VSYO 10 9 11 12 FSCO FSCI XOSO XOSI 13 14 20 21 22 23 24 VC VBLK VCNT VBSI VBSO SECAM NRE
BLOCK DIAGRAM
PD6464A,6465
Note
PD6464A only
PD6464A,6465
PIN CONFIGURATION (Top View)
24-pin plastic shrink DIP (300 mil)
PD6464ACS-xxx PD6465CS-xxx
24-pin plastic SOP (375 mil)
PD6464AGT-xxx PD6465GT-xxx
CLK CS DATA VDD OSCOUT OSCIN PCL GND FSCI FSCO XOSO XOSI
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VBSI VCNT SECAM VBSO NRE TEST N.C. CSYIN VSYO HSYO VBLK VC
Remark xxx: ROM code suffix (CS-001, GT-101: NEC standard device) CLK CS CSYIN DATA FSCI FSCO GND HSYO N.C. NRE OSCIN : Clock Input : Chip Select Input : Composite Synchronization Signal Input : Serial Data Input : fSC Signal Input : Frequency Error Output : Ground : Horizontal Synchronization Signal Output : No Connection : Noise Reduction Constant Append : LC Oscillation Input PCL TEST VBLK VBSI VBSO VC VCNT VDD VSYO XOSO XOSI : Power-on Clear : Test Pin : Blanking Signal Output : Composite Video Signal Input : Composite Video Signal Output : Character Signal Output : Video Signal Output Level Adjustment : Power Supply : Vertical Synchronization Signal Output : Quadruple Oscillation Output : Quadruple Oscillation Input
SECAM : SECAM subcarrier Input
OSCOUT : LC Oscillation Output
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PD6464A,6465
PIN FUNCTIONS
No. 1 2 Symbol CLK CS Clock input Chip select input Pin Name Function Inputs clock for data read. Data input to the DATA pin is read at the rising edge of the clock input to this pin. Serial transfer can be acknowledged by making this CS pin low.
3
DATA
Serial data input
Inputs control data. Data is read in synchronization with the clock input to the CLK pin. Supplies power to the IC. These are input and output pins of an oscillator that generates dot clocks. Connect a coil and a capacitor to these pins for oscillation. Power-ON clear pin. Make this pin high on power application. It initializes the internal circuitry of the IC. Ground pin of the IC. In case of the x4 multiplier, the color sub-carrier (fSC) is input to this pin. In case of the 4fSC Crystal oscillation, connect this pin to GND or VDD. The frequency error signal of the x4 multiplier is output to this pin. In case of the 4fSC Crystal oscillation, this pin should be open.
4 5 6 7
VDD OSCOUT OSCIN PCL
Power supply LC oscillation output LC oscillation input Power-ON clear
8 9
GND FSCI
Ground fSC signal input
10
FSCO
Frequency error output
11 12 13 14 15
XOSO XOSI VC VBLK HSYO
Quadruple oscillation output Quadruple oscillation input Character signal output Blanking signal output Horizontal synchronization signal output Vertical synchronization signal output
A quadruple oscillation LC for internal video signal generation is connected to these pins. A crystal oscillator can also be connected. Character signal output pin. Positive signal output. This pin outputs a blanking signal that cuts the video signal. It corresponds to the output of VC. Positive signal output. Outputs a horizontal synchronization signal separated from a composite synchronization signal. Outputs a vertical synchronization signal separated from a composite synchronization signal. A composite synchronization signal is input to this pin for synchronization signal separation. In case of the external signal mode, input the signal certainly. Input a positive synchronization signal. Non connection. Leave this pin open. Test mode select pin. Connect this pin to GND. Constant append pin for noise reduction. Outputs a composite video signal mixing a character signal. SECAM sub-carrier signal mixing pin. In cases of any system except for SECAM, this pin should be open. Adjusts the output level of the composite video signal and luminance signal. Inputs a composite video signal. Inputs a signal with the leading edge clamped, consisting of a negative synchronization signal and a positive video signal.
16
VSYO
17
CSYIN
Composite synchronization signal input
18 19 20 21 22
N. C. TEST NRE VBSO SECAM
Non connection Test pin Noise reduction constant append Composite video signal output SECAM subcarrier input
23
VCNT
Video signal output level adjustment Composite video signal input
24
VBSI
4
PD6464A,6465
CONTENTS
1. COMMANDS .................................................................................................................................... 1.1 Command Format ................................................................................................................. 1.2 Command List ....................................................................................................................... 1.3 Power-ON Clear Function .................................................................................................... 2. COMMAND DETAILS ..................................................................................................................... 2.1 Video RAM Batch Clear Command ..................................................................................... 2.2 Display Control Command ................................................................................................... 2.3 Internal Video Signal Color Control Command .................................................................. 2.4 Background Control Command ........................................................................................... 2.5 Internal/external Mode Control, Crystal Oscillation Control Command .......................... 2.6 Video Signal Method Control Command ............................................................................ 2.7 Oscillation Method Control Command ............................................................................... 2.8 Display Position Control Command .................................................................................... 2.9 Write Address Control Command ....................................................................................... 2.10 Output Level Control Command .......................................................................................... 2.11 Character Size Control Command ....................................................................................... 2.12 Test Mode Command ............................................................................................................ 2.13 Display Character Control Command (2-byte contiguous command) ............................ 3. TRANSFERRING COMMANDS ..................................................................................................... 3.1 1-Byte Command .................................................................................................................. 3.2 2-Byte Command .................................................................................................................. 3.3 2-Byte Contiguous Command ............................................................................................. 3.4 Successive Command Input ................................................................................................ 3.4.1 When 2-byte contiguous command end code is not used ..................................... 3.4.2 When 2-byte contiguous command end code is used ............................................ 3.5 BUSY Period for Command Input ........................................................................................ 3.5.1 When inputting 1-byte or 2-byte command .............................................................. 3.5.2 When inputting 2-byte contiguous command .......................................................... 4. ADJUSTING ..................................................................................................................................... 4.1 Adjusting Oscillation Frequency ......................................................................................... 4.1.1 Adjusting x4 multiplier and crystal oscillation frequency ...................................... 4.1.2 Adjusting LC oscillation frequency (dot clock) ....................................................... 4.2 Test Mode Clear Command .................................................................................................. 4.3 Clamp Level of Video Signal ................................................................................................
7 7 7 8 8 8 9 10 10 14 15 16 17 19 20 21 22 22 23 23 23 23 24 24 24 25 25 25 27 27 27 27 28 28
5. COMPOSITE SYNC. SIGNAL SEPARATION CIRCUIT ................................................................. 30 6. CHARACTER PATTERN DATA .................................................................................................... 32 6.1 Standard Character Patterns of the PD6464A .................................................................. 33 6.2 Standard Character Patterns of the PD6465 .................................................................... 36
5
PD6464A,6465
7. ELECTRICAL SPECIFICATIONS ................................................................................................... 42 8. APPLICATION CIRCUIT DIAGRAM ............................................................................................. 46 9. PACKAGE DRAWINGS ................................................................................................................. 48 10. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 50
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PD6464A,6465
1. COMMANDS
1.1 Command Format
Control commands are of variable length in 8-bit units and are input in serial. Three types of commands are available: 1-byte commands consisting of 8 bits of instruction and data in combination, 2-byte commands of 16 bits of instruction and data in combination, and a 2-byte contiguous command that can be abbreviated for input. Input command data from the MSB first.
1.2 Command List
1-byte commands
(MSB) Function Video RAM batch clear Display control Internal video signal color control Background control Internal/external mode control, crystal oscillation control Video signal method control Oscillation method control D7 0 0 0 0 0 D6 0 0 0 0 1 D5 0 0 1 1 0 D4 0 1 0 1 0 D3 0 D0 R 0 0 D2 0 LC G BS1 E/I D1 0 BL1 B BS0 0 D0 0 BL0 0 0 XOSC
0 0
1 1
0 0
0 1
1 0
N/P2 0
N/P1 Xfc
N/P0 0
2-byte commands
(MSB) Function Display position control Write address control Output level control Character size control Test mode
Note
D15 1 1 1 1 1
D14 0 0 0 0 0
D13 0 0 0 0 1
D12 0 0 1 1 1
D11 0 1 0 1 0
D10 0 0 0 0 0
D9 V4 0 0 0 0
D8 V3 AR3 VPD 0 0
D7 V2 AR2 0 0 T7
D6 V1 AR1 0 S0 T6
D5 V0 AR0 0 0 T5
D4 H4 AC4 0 0 T4
D3 H3 AC3 0 AR3 T3
D2 H2 AC2 1 AR2 T2
D1 H1 AC1 VC1 AR1 T1
D0 H0 AC0 VC0 AR0 T0
Note Must not be used. 2-byte contiguous command
(MSB) Function Display character control D15 1 D14 1 D13 0 D12 0 D11 0 D10 0 D9 BL D8 0 D7
Note
D6 C6
D5 C5
D4 C4
D3 C3
D2 C2
D1 C1
D0 C0
C7
Note Fixed to "0" (PD6464A)
7
PD6464A,6465
1.3 Power-ON Clear Function
Because the internal status of the IC is unstable on power application, initialize the IC by making the PCL pin high and executing a clear operation. When the clear operation has been performed, the following setting is made: * Test mode is cleared. * All the character data of the video RAM (12 lines, 24 columns) are set to display OFF data (7EH (PD6464A)/FEH (PD6465)) and the blinking data are set to OFF. * Video RAM write address (line 0, column 0) is set. * Character size is set to x1 (minimum) on all lines. * Display is turned OFF and LC oscillation is turned ON. The time required for the power-ON clear operation can be calculated by the following expression: t = tPCLL Note + {video RAM clear time} = 10 (s) + {10 (s) + 12/fOSC (MHz) x 288 [s]} Note Refer to 7. ELECTRICAL SPECIFICATIONS Power-ON Clear Specification. Remark fOSC: LC oscillation frequency (dot clock frequency)
2.
COMMAND DETAILS
2.1 Video RAM Batch Clear Command
This command can clear the video RAM with a single command.
D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
The video RAM batch clear command performs the following setting: * Sets all the character data of the video RAM (12 lines, 24 columns) to display OFF data (7EH (PD6464A)/FEH (PD6465)) and blinking data to OFF. * Sets a video RAM write address (line 0, column 0). * Sets the character size to x1 (minimum) on all lines. * Turns display OFF and LC oscillation ON. The time required for clearing the video RAM can be calculated by the following expression: t = video RAM clear time = 10 (s) + 12/fOSC (MHz) x 288 [s] Remark fOSC: LC oscillation frequency (dot clock frequency)
8
PD6464A,6465
2.2 Display Control Command
This command turns ON/OFF the display and controls LC oscillation and blinking of characters.
D7 0
D6 0
D5 0
D4 1
D3 D0
D2 LC
D1 BL1
D0 BL0
Blinking control bits BL1 0 0 1 1 BL0 0 1 0 1 Function Blinking OFF Blinking frequency: about 2 Hz Blinking frequency: about 1 Hz Blinking frequency: about 0.5 Hz
LC oscillation control bit LC 0 1 Function LC oscillation OFF LC oscillation ON Display ON/OFF control bit D0 0 1 Display OFF Display ON Function
* Blinking control bits These bits blink the character that is specified by the display character control command. The blinking ratio is 1:1, and three blinking frequencies can be selected. Blinking in character units can be specified by the display character control command. * LC oscillation control bit This bit controls LC oscillation and can turn ON/OFF the oscillation circuit. While no character is displayed, oscillation can be stopped to reduce the power dissipation. Data cannot be written to the video RAM with oscillation stopped. To write data to the video RAM, be sure to turn ON oscillation. Remark Oscillation is synchronized with Hsync when display is ON and LC oscillation is ON, and oscillation is stopped while Hsync is low. When display is OFF and LC oscillation is ON, oscillation is performed, regardless of the level of Hsync. * Display ON/OFF control bit This bit turns ON/OFF the display output. The display is turned ON/OFF in synchronization with the fall of Hsync.
9
PD6464A,6465
2.3 Internal Video Signal Color Control Command
This command sets the color of an internal video signal. The internal video signal is a video signal (e.g., blue back) internally generated by the PD6464A, 6465. While no external video signal is input to the PD6464A, 6465 and therefore no character can be displayed, if the internal video signal is selected, characters can be displayed.
D7 0
D6 0
D5 1
D4 0
D3 R
D2 G
D1 B
D0 0
Internal video signal color control bits R 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 Black Blue Green Setting prohibited Setting prohibited Setting prohibited Setting prohibited White Function
* Internal video signal color control bits These bits can select four colors as the color of the internal video signal.
2.4
Background Control Command
This command selects the background of the displayed character.
D7 0
D6 0
D5 1
D4 1
D3 0
D2 BS1
D1 BS0
D0 0
Background control bits BS1 0 0 1 1 BS0 0 1 0 1 Function No background Black framing Black-on-white Black filling
10
PD6464A,6465
* Background control bits These bits select the type of background in screen units from none, black-framed, black-on-white, or black-filled background. No background : Only character data are output. Black framing : If the left- and rightmost columns or the top and bottom lines of a dot matrix are not used, the displayed character can be framed horizontally, vertically, or diagonally. When the dots on the rightmost or leftmost column of the dot matrix are used, a frame is displayed in the adjacent character display areas. Even when the dots on the top and bottom lines of the dot matrix are used, the lines above and below the dot matrix are not framed. Even if the character size is changed, the size of black framing is fixed to 1 dot, which is the minimum size. Black-on-white : A black background is displayed on the rightmost and leftmost positions of the display area of the character written to the video RAM with 1 extra dot, which is the minimum size, at both positions. Black filling : A black background is displayed outside the character display area, in addition to the blackon-white background.,
11
PD6464A,6465
Display format in each background mode
No backgraund
Black framing
12 dots 1 dot
12 dots 1 dot 1 dot
Filling Note Data
Display Off Data
Filling Note Data
Display Off Data
Character (white) Image
Character (white) Framing (black) Image
Black-on-white 12 dots 1 dot 12 dots 1 dot 1 dot
Black filling
18 dots
10 dots 18 dots Filling Note Data Display Off Data Filling Note Data
10 dots
Display Off Data
Character (white) Image
Background (black)
Character (white) Image
Background (black)
Note Filling data means 1FH (PD6464A), 6EH (PD6465) with the NEC's standard character.
12
PD6464A,6465
Example of display when Display Off Data is used * Black-on-white background
Column
0 12 dots
1
20
21 12 dots
22 12 dots
23 12 dots
Display Off Data
18 dots
Display Off Data
Display Off Data
Display Off Data
Background output for 1 dot
Background output for 1 dot
External or internal video signal
Background output for 1 dot
The background color is output on 1 dot on both the edges of Display Off Data when the Display Off Data is used. * Black-filled background
Column
0 12 dots
1
20
21 12 dots
22 12 dots
23 12 dots
Display Off Data
18 dots
Display Off Data
Display Off Data
Display Off Data
Background
Background output for 1 dot
Background output for 1 dot
External or internal video signal
Background output for 1 dot
Background
The background color is output on 1 dot on both the edges of Display Off Data when the Display Off Data is used. Remark The "Background output for 1 dot" does not change by 1 dot, which is the minimum size, even when the character size is changed.
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PD6464A,6465
2.5 Internal/external Mode Control, Crystal Oscillation Control Command
This command selects the video signal with which a character signal overlaps (internal mode/external mode) and controls ON/OFF of crystal oscillation.
D7 0
D6 1
D5 0
D4 0
D3 0
D2 E/I
D1 0
D0 XOSC
Crystal oscillation control bit XOSC 0 1 Function Oscillation OFF Oscillation ON
Internal/external mode control bit E/I 0 1 Function External video signal mode Internal video signal mode
* Crystal oscillation control bit This bit controls oscillation of the crystal for internal video signal generation. When crystal oscillation is turned ON and the mode is changed from the external video signal mode to the internal video signal mode, the internal video signal is selected without the screen disturbed. When crystal oscillation is turned OFF, the synchronization separation circuit does not operate. Be sure to turn ON crystal oscillation. * Internal/external mode control bit External video signal mode : In this mode, character signals are output to the PD6464A and 6465, overlapping the external video signal that is input from external. The overlapped signal is output to the VBSO pin. If character signals should not be overlapped, set the display ON/OFF control bit to 0 (Display OFF) with the display control command. Moreover, a composite synchronization signal (Csync), which synchronizes with the video signal input from external, is required to be input from the CSYIN pin. If no Csync exists, input the composite synchronization signal generated from the input video signal via the composite sync signal separation circuit (refer to 5. COMPOSITE SYNC. SIGNAL SEPARATION CIRCUIT). In the timing generator block built in the PD6464A and 6465, a horizontal synchronization signal and a vertical synchronization signal are generated by separating from a composite synchronization signal synchronously. A reference signal is generated from these synchronous signals. The reference signal is used to reset and count the horizontal control block, vertical control block, and output control block. If Csync is not input, characters may not be displayed because the reference signal is not generated in the timing generator block. Internal video signal mode : In this mode, characters are output overlapping the video signal that is created in the PD6464A and 6465 (e.g., blue back signal) to the VBSO pin. In the internal video signal mode, characters can be displayed on the screen because horizontal and vertical synchronization signals are generated in a device, even if no composite synchronization signal is input.
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PD6464A,6465
2.6 Video Signal Method Control Command
The PD6464A, 6465 can select the NTSC, PAL, and PAL-M methods for the internal video signal. The PD6464A can also select the PAL-N method. When the SECAM method is selected, the internal video signal is output by the PAL method.
D7 0
D6 1
D5 0
D4 0
D3 1
D2 N/P2
Note
D1 N/P1
D0 N/P0
Video signal method control bits N/P2 0 0 0 0 1 N/P1 0 0 1 1 0 N/P0 0 1 0 1 0 NTSC PAL PAL-M SECAM PAL-N Function
Setting prohibited Note Fixed to "0" (PD6465).
* Video signal method control bits These bits can generate internal NTSC, PAL, PAL-M and PAL-N (PD6464A only) video signals. With the SECAM method, however, a color subcarrier from the SECAM color subcarrier input pin (pin 22) is fixed in the external mode. In the internal mode, an internal PAL video signal is generated. The internal video signal is generated by using a x4 multiplier or an external crystal. Use a crystal with a frequency of 4 fSC for each video signal.
15
PD6464A,6465
2.7 Oscillation Method Control Command
The PD6464A, 6465 can select a crystal for internal video signal generation or a x4 multiplier.
D7 0
D6 1
D5 0
D4 1
D3 0
D2 0
D1 Xfc
D0 0 Oscillation method control bit Xfc 0 1 Function Quadruple oscillation 4fSC crystal oscillation
* Oscillation method control bit In the PD6464A and 6465, the oscillation method can be selected from x4 multiplication oscillation and 4fSC crystal oscillation with the oscillation method control command. When x4 multiplication oscillation is selected, the fSC signal must be input from the FSCI pin. The 4fSC signal is generated from an external LC resonator and an internal circuit of the PD6464A and 6465. The phase of fourdivided 4fSC signal generated via LC oscillation is compared with that of the fSC signal that is input to the FSCI pin. The obtained phase error is converted to a voltage value, and then output from the FSCO pin. In the circuit shown in 8. APPLICATION CIRCUIT DIAGRAM (1) In x4 multiplication oscillation, the 4fSC signal synchronizing with the external fSC signal is generated by changing the capacitance of varactor diodes with this voltage that is based on a phase error. When 4fSC crystal oscillation is selected, the FSCI and FSCO pins are not used. These pins should be connected as follows. FSCI pin (pin 9) : Connect to GND or VDD.
FSCO pin (pin 10) : Leave open. Remark The scanning method in the internal video signal mode is non-interlacing. With the NTSC and PALM methods, the number of scanning lines is 263. With the PAL and PAL-N method, it is 312.
16
PD6464A,6465
2.8 Display Position Control Command
This command can set the display start position in 12-dot units and 32 steps in the horizontal direction, and in 9-line units and 32 steps in the vertical direction. Because this command is a 2-byte command, it must be input in 16-bit units even when the command is successively input.
D15 1
D14 0
D13 0
D12 0
D11 0
D10 0
D9 V4
D8 V3
D7 V2
D6 V1
D5 V0
D4 H4
D3 H3
D2 H2
D1 H1
D0 H0
Horizontal display start position control bit H4 0 0 H3 0 0 H2 0 0 H1 0 0 H0 0 1 Function From rising of Hsync (12 x 1)/fOSC+4/fOSC ( s) From rising of Hsync (12 x 2)/fOSC+4/fOSC ( s)
1
1
1
1
1
From rising of Hsync (12 x 32)/fOSC+4/fOSC ( s)
Remark fOSC: LC oscillation frequency (Dot Clock frequency) Vertical display start position control bit V4 0 0 V3 0 0 V2 0 0 V1 0 0 V0 0 1 Function From rising of Vsync 9H x 0 From rising of Vsync 9H x 1
1
1
1
1
1
From rising of Vsync 9H x 31
Remark H: Line
17
PD6464A,6465
* Horizontal display start position control bits The horizontal display start position can be set in 12-dot units and 32 steps, 16 clocks after the rising of the horizontal synchronization signal (Hsync) (16/fOSC (MHz)). * Vertical display start position control bits The vertical display start position can be set in 9-line units and 32 steps, from the rising of the vertical synchronization signal (Vsync).
Horizontal synchronization signal (Hsync)
A Display area (12 lines x 24 columns)
B
Vertical synchronization signal (Vsync)
A: 9H (line) x (2 4 V4 + 2 3V3 + 2 2 V2 + 2 1V1 + 2 0 V0) B: 12 fOSC (MHz) x (2 4H4 + 2 3 H3 + 22 H2 + 2 1H1 + 2 0 H0) + 16 fOSC (MHz)
Remark fOSC: LC oscillation frequency (Dot Clock frequency) Hsync and Vsync, which serve as references, are as follows: Internal video signal mode : Hsync and Vsync are generated by internal circuit. External video signal mode : Hsync and Vsync are generated from composite synchronization signal, input to CSYN pin (pin 17), by sync. signal separation circuit.
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PD6464A,6465
2.9 Write Address Control Command
This command specifies a write address when a character is written to the display area (video RAM) of 12 lines by 24 columns. Because this command is a 2-byte command, it must be input in 16-bit units even when input successively.
D15 1
D14 0
D13 0
D12 0
D11 1
D10 0
D9 0
D8 AR3
D7 AR2
D6 AR1
D5 AR0
D4 AC4
D3 AC3
D2 AC2
D1 AC1
D0 AC0
Write column address control bits AC4 0 0 AC3 0 0 AC2 0 0 AC1 0 0 AC0 0 1 Function Sets column 0 Sets column 1
1
0
1
1
1
Sets column 23
Setting prohibited Write line address control bits AR3 0 0 AR2 0 0 AR1 0 0 AR0 0 1 Function Sets line 0 Sets line 1
1
0
1
1
Sets line 11
Setting prohibited
* Write column address control bits One line consists of 24 columns in the horizontal direction. These bits specify the column to be written. * Write line address control bits One column consists of 12 lines in the vertical direction. These bits specify the line to be written. Video RAM configuration The video RAM consists of 12 lines by 24 columns as shown below. The number of display characters therefore is 12 lines by 24 columns (when all the lines are set to the minimum size).
AC4, AC3, AC2, AC1, AC0 AR3, AR2, AR1, AR0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 00000 00001 00010 10110 10111
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PD6464A,6465
2.10 Output Level Control Command
The PD6464A, 6465 can set the luminance level of the character and background (including the frame) by using a command. This command is a 2-byte command, and must be input in 16-bit units even when successively input.
D15 1
D14 0
D13 0
D12 1
D11 0
D10 0
D9 0
D8 VPD
D7 0
D6 0
D5 0
D4 0
D3 0
D2 1
D1 VC1
D0 VC0
Character level control bits VC1 0 0 1 1 VC0 0 1 0 1 Function Setting Prohibited 75 I.R.E. Setting Prohibited 90 I.R.E.
Internal video signal amplitude control bit VPD 0 1 Function 1 Vp-p amplitude 2 Vp-p amplitude
* Character level control bits These bits can select two character luminance levels: 75 or 90 I.R.E. If these bits are not set, the character level is set to 75 I.R.E. Remark The background (frame) level is fixed to 0 I.R.E. * Internal video signal amplitude control bit This bit sets the amplitude of the internal video signal to 1 or 2 Vp-p (this amplitude must match the amplitude of the signal input in the external video signal mode). When the amplitude is set to 1 Vp-p, the voltage applied to the VCNT pin must be 2.5 V. When the amplitude is set to 2 Vp-p, apply 5 V to the VCNT pin.
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PD6464A,6465
2.11 Character Size Control Command
This command can set the character size in line units (in both the horizontal and vertical directions). Because this is a 2-byte command, it must be input in 16-bit units even when successively input.
D15 1
D14 0
D13 0
D12 1
D11 1
D10 0
D9 0
D8 0
D7 0
D6 S0
D5 0
D4 0
D3 AR3
D2 AR2
D1 AR1
D0 AR0
Line specification control bits AR3 0 0 AR2 0 0 AR1 0 0 AR0 0 1 Function Sets line 0 Sets line 1
1
0
1
1
Sets line 11
Setting Prohibited
Character size control bit
1t dot = fOSC (MHz) s fOSC: LC oscillation frequency
1
S0 0 1
Function Vertical 1 dot: 1H, horizontal 1 dot: 1t dot (minimum size) Vertical 1 dot: 2H, horizontal 1 dot: 2t dots
* Line specification control bits These bits specify the character size in line units, and control which line is to be specified. * Character size control bit This bit selects the character size in two steps. Display with two character size specified
Example of display screen External video signal, etc.
Line 0: minimum size (vertical 18H/horizontal 12 dots) Line 1: 2 times (vertical 36H/horizontal 24 dots)
Line 2: minimum size Line 3: 2 times
Line 4: minimum size Line 5: 2 times
Line 6: 2 times Line 7: minimum size Lines 8 to 11 are omitted because they overflow from the screen.
The size in the vertical direction (the number of horizontal scanning lines) is the size in field units.
21
PD6464A,6465
2.12 Test Mode Command
This command is for testing the IC. Do not set this command.
D15 1 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 0 D7 T7 D6 T6 D5 T5 D4 T4 D3 T3 D2 T2 D1 T1 D0 T0
[Reference] Test mode clear command
D15 1 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
2.13
Display Character Control Command (2-byte contiguous command)
This command specifies the character data and blinking data to be written to the video RAM. When inputting this command, turn ON LC oscillation (if LC oscillation is turned OFF, no character can be written to the video RAM). Because this command is a 2-byte contiguous command, if character data are successively written without the blinking data changed, the second character and those that follow can be abbreviated to the lower 8 bits (D7 to D0). In this case, the write column address is automatically incremented (if a character is written to column 23 at the rightmost position, the next write address is automatically incremented to column 0 of the next line (leftmost position)).
Column address 0 1 2 22 23
Line address incremented Line address 0 1 2 10 11
D15 1
D14 1
D13 0
D12 0
D11 0
D10 0
D9 BL
D8 0
D7 C7
D6 C6
D5 C5
D4 C4
D3 C3
D2 C2
D1 C1
D0 C0
Character specification bits
Note 1
C7 0 0
C6 0 0
C5 0 0
C4 0 0
C3 0 0
C2 0 0
C1 0 0
C0 0 1
Function Outputs data of 00H Outputs data of 01H
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 1
Outputs data DISPLAY OFF
Note 2
End code of 2-byte contiguous command Note 3 Blink control bit
BL 0
Function Does not blink character Blinks character
Notes 1. Fixed to "0" (PD6464A). 2. 7EH (PD6464A), FEH (PD6465). 3. 7FH (PD6464A), FFH (PD6465).
1
22
PD6464A,6465
* Character specification bits These bits specify the address of a character. There are 128 types of characters available (PD6465: 256 types). Addresses 7EH (PD6464A), FEH (PD6465), 7FH (PD6464A) and FFH (PD6465), however, are fixed to the display OFF data and 2-byte contiguous command end code, respectively (no character can be set to these addresses even when the character is changed by mask code option because these addresses are fixed nevertheless). The character designs can be changed by mask code option. * Blink control bit This bit specifies whether the character written to the video RAM blinks, in character units. For the details of turning ON/OFF blinking in screen units, refer to 2.2 Display Control Command.
3. 3.1
TRANSFERRING COMMANDS 1-Byte Command
DATA CLK
CS
3.2
2-Byte Command
1st byte DATA 2nd byte 1st byte: D15-D8 2nd byte: D7-D0
CLK
CS
When transferring a 2-byte command, keep CS low between the first byte and second byte.
3.3
2-Byte Contiguous Command
1st byte DATA 2nd byte 2nd byte
CLK CS
The 2-byte contiguous command writes a character to the video RAM. To write characters in succession without changing the blink data, first transfer the first byte and then transfer the second bytes (character addresses) in succession.
23
PD6464A,6465
3.4 Successive Command Input
Transfer each of the 1-byte, 2-byte, and 2-byte contiguous commands from a microcomputer to the
PD6464A, 6465 as described below.
When transferring a 1-byte command, 2-byte command, or a 2-byte contiguous command with the blink data changed after a 2-byte contiguous command has been transferred, either make CS high once, or transfer end code of the 2-byte contiguous commandNote at the end of the 2-byte contiguous command. In the latter case, CS needs not to be made high. Note 7FH (PD6464A), FFH (PD6465)
3.4.1 When 2-byte contiguous command end code is not used Example 1-byte command 2-byte contiguous command 1-byte command
1-byte command 1st byte 1-byte command 2nd byte D7 - D0 normal characterNote D7 - D0
2-byte contiguous command 2nd byte D7 - D0 normal characterNote
DATA
D7 - D0
D15 - D8
CLK
CS CS must be made high once.
Note
00H-7EH (PD6464A), 00H-FEH (PD6465)
3.4.2 When 2-byte contiguous command end code is used Example 1-byte command 2-byte contiguous command 1-byte command
1-byte command 1st byte 1-byte command 2nd byte D7 - D0 2-byte contiguous command end code Note 2 D7 - D0
2-byte contiguous command 2nd byte D7 - D0 normal character Note 1
DATA
D7 - D0
D15 - D8
CLK
CS CS needs not to be made high.
Notes 1. 00H-7EH (PD6464A), 00H-FEH (PD6465) 2. 7FH (PD6464A), FFH (PD6465) Remark Although the CS pin can remain low when the end code of the 2-byte contiguous command is used, making this pin high is recommended as a countermeasures against noise.
24
PD6464A,6465
3.5 BUSY Period for Command Input
The BUSY period for command input is distinguished depending on whether a 1-byte, 2-byte, or 2-byte contiguous command is used. When inputting 2-byte contiguous command, there are two timings as shown below, (1) Not transferring 2byte contiguous command in Vsync period with detecting Vsync and (2) Transferring 2-byte contiguous command in Vsync period without detecting Vsync. When inputting commands in succession, observe the following timing: 3.5.1 When inputting 1-byte or 2-byte command
CLK
TB1
Parameter Command continuous input enable time 1
Symbol TB1
Condition 1-byte or 2-byte command
MIN. 2.0
TYP.
MAX.
Unit
s
3.5.2 When inputting 2-byte contiguous command (1) Not transferring 2-byte contiguous command in Vsync period with detecting Vsync (command continuous input enable time 2 = TB2)
CLK TB1' TB2
Parameter Command continuous input enable time 2
Symbol TB2
Condition 2-byte contiguous command (= video RAM write command)
MIN. Display ON TB1' + (21/fOSC) x S1 + THWL1 Display OFF TB1' + (21/fOSC) x S1
TYP. MAX. Unit
s
Remark fOSC S1
: clock frequency of LC oscillation : character size
THWL1 : Hsync width TB1' 2.0 s
25
PD6464A,6465
(2) Transferring 2-byte contiguous command in Vsync period without detecting Vsync (command continuous input enable time 2' = TB2')
CLK
TB2'
Parameter Command continuous input enable time 2'
Symbol TB2'
Condition 2-byte contiguous command (= video RAM write command), Display ON
MIN. (21/fOSC) x S2 + THWL2
TYP. MAX. Unit
s
Remark fOSC S2
: clock frequency of LC oscillation : character size of the first line
THWL2 : Hsync period
26
PD6464A,6465
4. ADJUSTING
This section describes how to adjust each circuit of the PD6464A, 6465. When performing adjustment, the TEST pin (pin 19) must be connected to VCC.
4.1
4.1.1
Adjusting Oscillation Frequency
Adjusting x4 multiplier and crystal oscillation frequency
The PD6464A, 6465 generate the internal video signal by means of quadruple oscillation of 4fSC or crystal oscillation. The oscillation frequency of 4fSC can be output from the VSYO pin (pin 16) by using the test mode command. Adjustment * Connect the TEST pin (pin 19) to VCC (normally, connect this pin to GND). * Input the following command. The quadrupled or crystal oscillation frequency will be output from the VSYO pin (pin 16). To clear the test mode, either transfer the test mode clear command, or connect the TEST pin to GND. * In this case, the VSYO pin does not function as a vertical synchronization signal output pin. * Adjust the frequency with a capacitor (or coil), connected to XOSI pin (pin 12), shown in 8. APPLICATION CIRCUIT DIAGRAM using a frequency counter. Crystal oscillation frequency output command (2-byte command)
D15 1 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 1 D4 1 D3 1 D2 1 D1 1 D0 1
4.1.2
Adjusting LC oscillation frequency (dot clock)
The PD6464A, 6465 create the dot clock of characters by means of LC oscillation. The LC oscillation frequency can be output from the HSYO pin by using the test mode command, in the same manner as when adjusting the crystal oscillation frequency described in 4.1.1. Adjustment * Connect the TEST pin (pin 19) to VCC (normally, connect this pin to GND). * Input the following command. The LC oscillation frequency will be output from HSYO pin (pin 15). To adjust the LC oscillation frequency, turn OFF display. When display is ON and while Hsync is low, oscillation is stopped and the accurate oscillation frequency cannot be obtained (when using a frequency counter). To clear the test mode, either transfer the test mode clear command, or connect the TEST pin to GND. * In this case, the HSYO pin does not function as a horizontal synchronization signal output pin. * Adjust the frequency with a trimmer capacitor (or coil), connected to OSCIN pin (pin 6) shown in 8. APPLICATION CIRCUIT DIAGRAM using a frequency counter. LC oscillation frequency output command (2-byte command)
D15 1 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 1 D4 1 D3 1 D2 1 D1 1 D0 1
27
PD6464A,6465
4.2 Test Mode Clear Command
The command that clears the test mode is as follows:
D15 1 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0
Caution
Be sure to connect the TEST pin to VCC when performing the above adjustment. Be sure to connect the TEST pin to GND after adjustment.
4.3
Clamp Level of Video Signal
Match the clamp level of the composite video signal input to the PD6464A, 6465 with the internal video signal level of the PD6464A, 6465. Otherwise, the character level in the external video signal mode will differ from that in the internal video signal mode. Adjustment The internal video signal level of the PD6464A, 6465 is set by the voltage applied to the VCNT pin and an "output level control command". The amplitude level of the internal video signal, sync-chip level, and pedestal level can be set in the following combination:
Specified by Output Level Control Command Selects 1 Vp-p Selects 2 Vp-p Internal Video Signal Amplitude Level (VDD = 5.0 typ.) 1 Vp-p 2 Vp-p Sync-Chip Level (VDD = 5.0 typ.) (VSYT) 1V 1V Pedestal Level (VDD = 5.0 typ.) (VPED) 1.29 V 1.58 V
VCNT Pin Voltage
2.5 V 5.0 V
Adjust the sync-chip and pedestal levels of the external video signal to the same level of the internal video signal by using a variable resistor (pin 23) shown in 8. APPLICATION CIRCUIT DIAGRAM. When setting the video amplitude level to 1 Vp-p, connecting a variable resistor to the VCNT pin is recommended to adjust the internal video signal level (when setting the video signal to 2 Vp-p, connect the VCNT pin to the power supply (5 V)).
28
PD6464A,6465
VSYT and VPED levels of composite video signal
VSYT GND
VPED
Match the level output from the VBSI pin in the external video signal mode with the level output from the same pin in the internal video signal mode. Input level in external video signal mode (when video signal of 1 Vp-p is input)
5V RVCNT Voltage applied to VCNT pin by RVCNT = 2.5 V
VCNT VSYT = 1.0 V clamp input VBSI VBSO
To input an external video signal with an amplitude of 2 Vp-p, input a 1.0-V clamp signal to VSYT, apply 5.0 V to the VCNT pin, and set the amplitude of 2 Vp-p by using the "output level control command".
29
PD6464A,6465
5. COMPOSITE SYNC. SIGNAL SEPARATION CIRCUIT
An example of composite sync. signal separation circuit is shown in Figure 5-1. Figure 5-1. Composite Sync. Signal Separation Circuit (a) Example of Composite Sync. Signal Separation Circuit
VDD = 5 V R6 c R1 Composite video signal (2 Vp-p) C1 + R2 a b Q1 + C2 IX R5 C3 R8 R9 R3 VC Isp R4 Q2 Input to pin 17 0.3 VDD (MAX.) Q3 R7 Composite sync. signal (sync. positive) 0.7 VDD (MIN.)
R1 = 5.1 k, R2 = 1.2 k, R3 = 1 k, R4 = 220 , R5 = 100 k, R6 = 10 k, R7 = 1 k, R8 = 2.2 k, R9 = 10 k, C1 = 10 F, C2 = 1 F, C3 = 1000 pF (b) Image of sync. signal separation waveform
T1
T2
T1 = 4.7 s T2 = 58.86 s
VC VC1 VC3 VC2
The slice level (VS) of Figure 5-1 (a) is defined as follows. R5 R4 T2 T1 . 74 mV = .
VS = 2.7 x
x
30
PD6464A,6465
When VS is small, it is suited for horizontal sync. separation, but is against to vertical sync. separation. And when VS is large, edge noise of horizontal sync. separation causes a synchronization error (jitter). Therefore, the constant of each element in the circuit should be optimized according to input signal's characteristics. The C2 capacitance should be specified as a sufficient larger value compared to charge/discharge current. If the value overly exceeds the suitable value, however, excessive response characteristics will be inferior, falling to trace rapid average-picture-level (APL) fluctuation of input signal. In the circuit shown in Figure 5-1 (a), a capacitor is connected to the composite video signal input portion for measurement. However, this makes it hard to trace APL fluctuation. Therefore, in designing an actual circuit, insert a sync-chip clamp in front of Q1 in Figure 5-1 (a). to stabilizes the potential of a synchronization signal, for tracing APL fluctuation. Caution In the circuit of Figure 5-1 (a), the width of the Hsync synchronization signal that is included in the composite synchronization signal after separation may be wider than that of the Hsync synchronization signal that is included in the input video signal, because of its circuit configuration. Therefore, the width of the Hsync synchronization signal during a command continuous input enable time (refer to 3.5 BUSY Period for Command Input) should be the same as that of the Hsync synchronization signal included in Csync after separation in the circuit of Figure 5-1 (a).
31
PD6464A,6465
6. CHARACTER PATTERN DATA
The only difference between the PD6464ACS-001 and PD6464AGT-101 is the package. The character patterns in the character ROMs of both the models are the same. The same applies to the PD6465CS-001 and the PD6465GT-101. Both the PD6464ACS-001 and PD6464AGT-101 can display 128 types of alphanumeric characters and character patterns such as Kanji, Hiragana, and Katakana. The PD6465CS-001 and PD6465GT-101 can display 256 types of them. The contents of the character ROM (character design) can be changed by mask code option. However, the characters at addresses 7EH and 7FH (PD6464A)/FEH and FFH (PD6465) are fixed to [Display Off Data] and [2-byte contiguous command end code], respectively, and no character patterns can be set to these addresses. Although 10H (PD6464A)/6FH (PD6465) (Blank Data) and 7EH (PD6464A)/FEH (PD6465) (Display Off Data) of the NEC's standard model are represented in the same manner in the page showing the character patterns (i.e., these are shown as characters without dots), they have the following differences:
Display of Part to Which Character Is Written in Each Mode Video Signal Mode Character CodeNote No background External video signal mode Blank Data Display Off Data Displays external video signal Background Black-on-white Displays background Displays external video signal (without background) Internal video signal mode Blank Data Display Off Data Displays internal video signal color Displays background Displays internal video signal color Black filling Displays background Displays external video signal (without background) Displays background Displays internal video signal color
You cannot specify Display Off Data for addresses other than 7EH (PD6464A)/FEH (PD6465) when using a mask option. Blank Data, however, can be specified at any address from 00H to 7DH (PD6464A)/FDH (PD6465) (address 7FH (PD6464A)/FFH (PD6465) cannot be used because it contains the end code for second-byte continuous input). The character patterns of the PD6464ACS-001 and GT-101/PD6465CS-001 and GT-101 (NEC's standard models) are shown on the following pages.
32
PD6464A,6465
6.1
00 H
Standard Character Patterns of the PD6464A
01 H 02 H 03 H 04 H 05 H 06 H 07 H
08 H
09 H
0A H
0B H
0C H
0D H
0E H
0F H
10 H Note
11 H
12 H
13 H
14 H
15 H
16 H
17 H
18 H
19 H
1A H
1B H
1C H
1D H
1E H
1F H
20 H
21 H
22 H
23 H
24 H
25 H
26 H
27 H
28 H
29 H
2A H
2B H
2C H
2D H
2E H
2F H
Note
Blank Data
33
PD6464A,6465
30 H
31 H
32 H
33 H
34 H
35 H
36 H
37 H
38 H
39 H
3A H
3B H
3C H
3D H
3E H
3F H
40 H
41 H
42 H
43 H
44 H
45 H
46 H
47 H
48 H
49 H
4A H
4B H
4C H
4D H
4E H
4F H
50 H
51 H
52 H
53 H
54 H
55 H
56 H
57 H
58 H
59 H
5A H
5B H
5C H
5D H
5E H
5F H
34
PD6464A,6465
60 H
61 H
62 H
63 H
64 H
65 H
66 H
67 H
68 H
69 H
6A H
6B H
6C H
6D H
6E H
6F H
70 H
71 H
72 H
73 H
74 H
75 H
76 H
77 H
78 H
79 H
7A H
7B H
7C H
7D H
7E H Note 1
7F H Note 2
Notes 1. Display Off Data (character address fixed) 2. End code of 2-byte contiguous command (character address fixed)
35
PD6464A,6465
6.2 Standard Character Patterns of the PD6465
00 H 01 H 02 H 03 H 04 H 05 H 06 H 07 H
08 H
09 H
0A H
0B H
0C H
0D H
0E H
0F H
10 H
11 H
12 H
13 H
14 H
15 H
16 H
17 H
18 H
19 H
1A H
1B H
1C H
1D H
1E H
1F H
20 H
21 H
22 H
23 H
24 H
25 H
26 H
27 H
28 H
29 H
2A H
2B H
2C H
2D H
2E H
2F H
36
PD6464A,6465
30 H
31 H
32 H
33 H
34 H
35 H
36 H
37 H
38 H
39 H
3A H
3B H
3C H
3D H
3E H
3F H
40 H
41 H
42 H
43 H
44 H
45 H
46 H
47 H
48 H
49 H
4A H
4B H
4C H
4D H
4E H
4F H
50 H
51 H
52 H
53 H
54 H
55 H
56 H
57 H
58 H
59 H
5A H
5B H
5C H
5D H
5E H
5F H
37
PD6464A,6465
60 H
61 H
62 H
63 H
64 H
65 H
66 H
67 H
68 H
69 H
6A H
6B H
6C H
6D H
6E H
6F H Note
70 H
71 H
72 H
73 H
74 H
75 H
76 H
77 H
78 H
79 H
7A H
7B H
7C H
7D H
7E H
7F H
80 H
81 H
82 H
83 H
84 H
85 H
86 H
87 H
88 H
89 H
8A H
8B H
8C H
8D H
8E H
8F H
Note
Blank Data
38
PD6464A,6465
90 H
91 H
92 H
93 H
94 H
95 H
96 H
97 H
98 H
99 H
9A H
9B H
9C H
9D H
9E H
9F H
A0 H
A1 H
A2 H
A3 H
A4 H
A5 H
A6 H
A7 H
A8 H
A9 H
AA H
AB H
AC H
AD H
AE H
AF H
B0 H
B1 H
B2 H
B3 H
B4 H
B5 H
B6 H
B7 H
B8 H
B9 H
BA H
BB H
BC H
BD H
BE H
BF H
39
PD6464A,6465
C0 H
C1 H
C2 H
C3 H
C4 H
C5 H
C6 H
C7 H
C8 H
C9 H
CA H
CB H
CC H
CD H
CE H
CF H
D0 H
D1 H
D2 H
D3 H
D4 H
D5 H
D6 H
D7 H
D8 H
D9 H
DA H
DB H
DC H
DD H
DE H
DF H
E0 H
E1 H
E2 H
E3 H
E4 H
E5 H
E6 H
E7 H
E8 H
E9 H
EA H
EB H
EC H
ED H
EE H
EF H
40
PD6464A,6465
F0 H
F1 H
F2 H
F3 H
F4 H
F5 H
F6 H
F7 H
F8 H
F9 H
FA H
FB H
FC H
FD H
FE H Note 1
FF H Note 2
Notes 1. Display Off Data (character address fixed) 2. End code of 2-byte contiguous command (character address fixed)
41
PD6464A,6465
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Input pin voltage Output pin voltage Permissible package power dissipation (TA = 75 C) Operating ambient temperature Storage temperature Output current Symbol VDD VIN VOUT PD 470
PD6464ACS, 6465CS
7
PD6464AGT, 6465GT
Unit V V V
-0.3 to VDD +0.3 -0.3 to VDD +0.3 320
mW C C mA
TA Tstg IO
-20 to +75 -40 to +125 5
Caution
Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics.
Recommended Operating Conditions
Parameter Supply voltage Operating ambient temperature LC oscillation frequency Control input high level voltage Control input low level voltage Signal output high level voltage Signal output low level voltage Internal signal level setting voltage External video signal input voltage Current consumption Symbol VDD TA fOSC VCIH VCIL VSOH VSOL VVL Vi IDD DATA, CLK, CS, PCL DATA, CLK, CS, PCL ISOH=-1mA, VDD=5.0 V ISOL=1mA, VDD=5.0 V VCNT VBSI fOSC=8MHz 2.5 0 4.5 0.5 VDD VDD 20 Conditions MIN. 4.5 -20 4 3.5 1.5 7 TYP. 5.0 MAX. 5.5 +75 8 Unit V C MHz V V V V V V mA
42
PD6464A,6465
AC Characteristics (Unless otherwise specified, VDD = 5 V, TA = +25 C)
Parameter Synchronization signal input pulse width Pedestal level voltage Sync-chip level voltage Color burst high level voltage 1 Color burst low level voltage 1 Color burst high level voltage 2 Color burst low level voltage 2 Black level voltage Blue VBS high level voltage Blue VBS low level voltage Green VBS high level voltage Green VBS low level voltage White level voltage Burst phase angle Green phase angle Blue phase angle Burst phase angle Green phase angle Blue phase angle Burst phase angle Green phase angle Blue phase angle Crystal oscillation frequency 1 Crystal oscillation frequency 2 Crystal oscillation frequency 3 Crystal oscillation frequency 4 Character 90% level voltage Character 75% level voltage Background 0% level voltage fSC input amplitude Symbol tHST Conditions MIN. 4.0 TYP. MAX. 9.0 Unit
s
V V V V V V V V V V V V deg deg deg deg deg deg deg deg deg MHz MHz MHz MHz
VPED VSYT VCBH1 VCBL1 VCBH2 VCBL2 VBLA VBLH VBLL VGRH VGRL VWHI
VBSO, internal mode, VCNT = 2.5 V, VSYT = 1.0 V
1.03 0.8 1.15 0.91 1.20 0.85 1.03 1.26 0.88 1.53 1.03 1.45
1.29 1.0 1.44 1.14 1.50 1.07 1.29 1.58 1.11 1.92 1.29 1.82 180 225 0 135 225 0 225 135 0 14.31818 17.734475 14.302446 14.328225
1.55 1.20 1.73 1.37 1.80 1.28 1.55 1.90 1.34 2.31 1.55 2.19 190 235 10 145 235 10 235 145 10
BSC G B BSC1 G1 B1 BSC2 G2 B2
fXON1 fXON2 fXON3 fXON4 V90 V75 V0 fin
NTSC, internal mode
170 215 350
PAL1, internal mode
125 215 350
PAL2, internal mode
215 125 350
In NTSC mode In PAL, SECAM mode In PAL-M mode In PAL-N mode VCNT = 2.5 V, VSYT = 1.0 V 1.53 1.45 VCNT = 2.5 V, VSYT = 1.0 V 1.03 300
1.92 1.82 1.29
2.31 2.19 1.55
V V V mVp-p
43
PD6464A,6465
Concept of PD6464A, 6465 internal video signal level
VGRH
VWHI
VBLH
VCBH VPED VCBL VBLL VSYT VGRL VBLA
GND
44
PD6464A,6465
Recommended Operation Timing (TA = -20 to +75 C, VDD = 4.5 to 5.5 V)
Parameter Setup time Hold time Minimum clock low-level width Minimum clock high-level width Clock cycle CS setup time CS hold time CLK slew rate Symbol tSET tHOLD tCKL tCKH tTCK tCSS tCSH tCSR Conditions MIN. 200 200 400 400 1.0 400 400 100 TYP. MAX. Unit ns ns ns ns
s
ns ns ns
90 % DATA 10 % tSET tHOLD
CLK
90 % tCSS
10 % tCKL tCSR tTCK 90 % tCKH
CS tCSH
Power-ON Clear Specification
Parameter PCL pin low-level hold period Symbol tPCLL Conditions MIN. 10 TYP. MAX. Unit
s
VDD
0.9 VDD
VDD
0V
tPCLL VDD PCL 0.1 VDD 0V
45
PD6464A,6465
8. APPLICATION CIRCUIT DIAGRAM
(1) x4 multiplier oscillation
<> 5.1 k
VCC = 5 V 2.2 k
Video-IN
10 F
+
2 Vp-p
1.2 k
100 k
VCC = 5 V 1 CLK 2 CS VDD = 5 V 3 DATA 1 2 3 4 30 pF 5 39 H 6 5 to 30 pF + 300 mVp-p (min) fSC input 2200 pF + 1 F 1.5 k
100 kW 1000 pF VD
CLK CS DATA VDD OSCOUT OSCIN PCL GND FSCI FSCO XOSO XOSI
VBSI VCNT SECAM VBSO NRE TEST N. C. CSYIN VSYO HSYO VBLK VC
24 VCC = 5 V 23 100 pF 22 10 H 2 Vp-p 21 100 pF 20 19 18 Csync 17 16 15 14 13 2.2 k Video OUT
+
10 F
0.01 F
10 F
7 8
0.01 F 5.1 k
9 10 11 4.7 H 12
18 pF
47 pF NTSC, PAL-M: H PAL, SECAM : L
20 k 20 k
Cautions 1. The clamp circuit is not necessary when the sync-chip level (1 V DC) can be directly input to pin 24. 2. Pin 20 is connected so as to reject unwanted radiation. 3. This application circuit is assumed to input 2Vp-p video signals. 4. Product equivalent to 1SV163 can be used as a VD (Varactor diode).
46
PD6464A,6465
(2) 4fSC Crystal oscillation
<> 5.1 k
VCC = 5 V 2.2 k
Video-IN
10 F
+
2 Vp-p
1.2 k
100 k
VCC = 5 V 1 CLK 2 CS VDD = 5 V 3 DATA 1 2 3 4 30 pF 5 39 H 6 5 to 30 pF + 10 F 7 8 VDD or GND open 30 pF 11 4 fSC 12 5 to 30 pF XOSI VC 13 XOSO VBLK 14 9 10 PCL GND FSCI FSCO N. C. CSYIN VSYO HSYO 18 Csync 17 16 15 OSCIN TEST 19 OSCOUT NRE 20 CLK CS DATA VDD VBSI VCNT SECAM VBSO 24 VCC = 5 V 23 100 pF 22 10 H + 10 F 0.01 F 21 100 pF 2 Vp-p 2.2 k Video OUT
Cautions 1. The clamp circuit is not necessary when the sync-chip level (1 V DC) can be directly input to pin 24. 2. Pin 20 is connected so as to reject unwanted radiation. 3. This application circuit is assumed to input 2Vp-p video signals. 4. Connect pin 9 to GND or VDD (do not open). Pin 10 should be open.
47
PD6464A,6465
9. PACKAGE DRAWINGS
24 PIN PLASTIC SHRINK DIP (300 mil)
24 13
1
A
12
J I
K L
F D H G N
M
C
B M R
NOTES 1. Controlling dimension millimeter.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 21.950.2 1.78 MAX. 1.778 (T.P.) 0.500.10 0.85 MIN. 3.20.3 0.51 MIN. 3.450.2 5.08 MAX. 7.62 (T.P.) 6.40.2 0.25 +0.10 -0.05 0.17 0~15
INCHES 0.864 +0.009 -0.008 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.033 MIN. 0.1260.012 0.020 MIN. 0.136 +0.008 -0.009 0.200 MAX. 0.300 (T.P.) 0.2520.008 0.010 +0.004 -0.003 0.007 0~15 S24C-70-300B-2
2. Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 3. Item "K" to center of leads when formed parallel.
48
PD6464A,6465
24 PIN PLASTIC SOP (375 mil)
24 13
detail of lead end
P
1 A F G
12
H I J
L C D E
NOTE 1. Controlling dimention
millimeter.
S
M
K
M
B N S
ITEM A B C D E F G H I J K L M N P MILLIMETERS 15.3 +0.41 -0.2 0.87 MAX. 1.27 (T.P.) 0.42 +0.08 -0.07 0.1250.075 2.9 MAX. 2.500.2 10.30.2 7.20.2 1.60.2 0.17 +0.08 -0.07 0.80.2 0.12 0.10 3 +7 -3 INCHES 0.602 +0.017 -0.008 0.035 MAX. 0.050 (T.P.) 0.017 +0.003 -0.004 0.0050.003 0.115 MAX. 0.098 +0.009 -0.008 0.406 +0.008 -0.009 0.283 +0.009 -0.008 0.0630.008 0.007 +0.003 -0.004 0.031+0.009 -0.008 0.005 0.004 3+7 -3 P24GT-50-375B-2
2. Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
49
PD6464A,6465
10. RECOMMENDED SOLDERING CONDITIONS
Solder the PD6464A, 6465 under the conditions shown below. For the details of the recommended soldering conditions, refer to "Semiconductor Device Mounting Technology Manual" (C10535E). For other soldering methods and conditions, consult NEC. Surface mount devices
PD6464AGT-xxx: 24-pin plastic SOP (375 mil) PD6465GT-xxx: 24-pin plastic SOP (375 mil)
Process Infrared ray reflow Conditions Peak temperature: 235 C or below (Package surface temperature), Reflow time: 30 seconds or less (at 210 C or higher), Maximum number of reflow processes: 2 times, Peak temperature: 215 C or below (Package surface temperature), Reflow time: 40 seconds or less (at 200 C or higher), Maximum number of reflow processes: 2 times, Solder temperature: 260 C or below, Flow time: 10 seconds or less, Maximum number of flow processes: 1 time, Pre-heating temperature: 120 C or below (Package surface temperature), Partial heating method Pin temperature: 300 C or below, Heat time: 3 seconds or less (Per each side of the device). -- Symbol IR35-00-2
Vapor Phase Soldering
VP15-00-2
Wave Soldering
WS60-00-1
Caution
Apply only one kind of soldering condition to a device, except for "partial heating method", or the device will be damaged by heat stress.
Through-hole devices
PD6464ACS-xxx: 24-pin plastic shrink DIP (300 mil) PD6465CS-xxx: 24-pin plastic shrink DIP (300 mil)
Process Wave soldering (only to leads) Partial heating method Solder temperature: 260 C or below, Flow time: 10 seconds or less. Pin temperature: 300 C or below, Heat time: 3 seconds or less (Per each lead). Conditions
Caution
For through-hole devices, the wave soldering process must be applied only to leads, and make sure that the package body does not get jet soldered.
50
PD6464A,6465
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
51
PD6464A,6465
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

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